The present invention is concerned with a semiconductor device and a method of forming the same, and more specifically relates to a semiconductor device having a dual gate and a method of forming the same.
In general, a CMOS (Complementary Metal Oxide Silicon) semiconductor device includes an NMOS (N-channel Metal Oxide Silicon) transistor and a PMOS (P-channel Metal Oxide Silicon) transistor. Electrons are accumulated in a channel of the NMOS transistor, and holes are accumulated in a channel of the PMOS transistor.
A method for forming gate electrodes of the NMOS and PMOS transistors with polysilicon doped with n-type impurities is disclosed. In accordance with this method, productivity can be improved by simplifying a fabrication process, but a channel of the PMOS transistor may be a buried channel because a work function of polysilicon doped with n-type impurities is close to a silicon conduction-band edge energy level. As a result, an operation speed of the PMOS transistor may be decreased.
With high integration of semiconductor devices, there has been an increasing need for a PMOS transistor and an NMOS transistor to be operated at high speed. To obtain PMOS and NMOS transistors with high speed and optimized characteristics, a PMOS gate electrode and an NMOS gate electrode are generated to have optimized work functions. That is, a work function of the NMOS gate electrode is close to a silicon conduction-band edge energy level, and a work function of the PMOS gate electrode is close to a silicon valence-band edge energy level. In this case, all channels of the NMOS and PMOS transistors may be formed of a surface channel. Accordingly, the NMOS and PMOS transistors can be operated at high speed.
Formation of an NMOS gate electrode with polysilicon doped with n-type impurities and a PMOS gate electrode with polysilicon doped with p-type impurities has been proposed. In this method, work functions of the PMOS and NMOS transistors are close to a silicon conduction-band edge energy level and a silicon valence-band edge energy level, respectively, so that they can be operated at high speed. In case where the NMOS and PMOS transistors are formed of polysilicon doped with n-type or p-type impurities, however, a depletion region is formed in the gate electrodes of the NMOS and PMOS transistors. As a result, operation speed of the NMOS and PMOS transistors may be decreased.
Thus, a semiconductor device having a dual gate electrode for optimizing characteristics, e.g., high-speed and/or low power consumption, of NMOS and PMOS transistors is being investigated very actively.